AMD has started the volume production ramp of its sixth-generation EPYC server processor, codenamed "Venice," on TSMC's 2nm (N2) process — making it the first high-performance computing product in the industry to reach production on the node. Venice scales to 256 Zen 6 cores and, per figures reported alongside the ramp, delivers roughly 70% more compute than the current "Turin" generation. AMD says commercial shipments arrive later in 2026.
The ramp is running in Taiwan first, with a later production stage planned at TSMC's Arizona fab.
The host side of the AI cluster
Venice is a general-purpose server CPU, not an accelerator — but in an AI data center the EPYC host is what feeds the GPUs. It schedules work, moves data between storage, network and accelerator memory, and runs the orchestration layer for agentic pipelines that fan requests across tool calls and retrieval. AMD frames Venice squarely at "increasingly complex agentic workloads" where the CPU coordinates data movement, networking and storage for the accelerators around it.
Reported platform specs back that positioning: a new SP7 socket, up to 16 DDR5 memory channels delivering around 1.6 TB/s of per-socket bandwidth, and doubled CPU-to-GPU bandwidth versus the prior generation. Memory bandwidth at the host is precisely where mixed inference and retrieval clusters tend to stall.
First to 2nm, and the Intel gap
Being first to volume on N2 is the strategic headline. "Ramping 'Venice' on TSMC 2nm process technology marks an important step forward in accelerating the next generation of AI infrastructure," said AMD chair and CEO Lisa Su. TSMC chairman and CEO C.C. Wei said the collaboration reflects "pairing leadership process technology with advanced design innovation to enable the next era of high-performance and AI computing."
The timing favors AMD. Intel's competing P-core Xeon, "Diamond Rapids," is reportedly delayed toward mid-2027 — meaning AMD could hold the leading-edge node largely uncontested in the high-core-count server tier through the next procurement cycle.
Verano and the agentic-memory bet
AMD also confirmed it will extend TSMC 2nm across the data center roadmap with "Verano," a follow-on sixth-gen EPYC part tuned for performance-per-dollar-per-watt. Notably, Verano integrates LPDDR — AMD's bet that memory capacity and efficiency, not just core count, become the constraint for agentic AI workloads running long, tool-heavy contexts.
What changes for builders
For infra teams sizing 2026–2027 fleets, the practical signal is twofold: host-side capacity and bandwidth are scaling to match GPU density, and the leading-edge node now carries an efficiency story (perf-per-watt, perf-per-dollar) that feeds directly into cluster TCO. With Intel's high-end server refresh slipping, buyers planning GPU build-outs have a clearer near-term default for the head nodes — and a reason to revisit power and rack budgets before the Venice and Verano parts land in volume.
